This application claims priority under 35 USC xc2xa7119(e)(1) of United Kingdom Application Number GB 0013790.1, filed Jun. 6, 2000.
1. Technical Field of the Invention
This invention relates generally to flip flop design, and more particularly to designs for high performance flip-flops.
2. Background of the Invention
FIGS. 1 to 4 relate to a known scannable flip-flop. A circuit symbol 1 for the device is given in FIG. 1. The flip-flop has data inputs D and SD, control inputs ScanZ and CLK and outputs Q, QZ and SQ. (In this description, the letter Z will denote an inverted signal, so that the output QZ is the inverse of the output Q.) In practice for testing purposes many such flip-flops are linked together in a shift register with the SQ output of each being connected to the SD input of the next.
The circuit schematic for the known scannable flip-flop is given in FIG. 2. The SD and D inputs are coupled to the input of a multiplexer 2, that multiplexer comprising two tristate inverters 3 and 4. Tristate inverter 3 inverts the D input when the ScanZ input is high (i.e. when Scan is low) and is high impedance when ScanZ is low. Conversely, tristate inverter 4 inverts the SD input when ScanZ is low and is high impedance when ScanZ in high. Thus the output of the multiplexer 2 is either DZ (the inverse of D) or SDZ (the inverse of SD) dependent on the Scan input.
The output of the multiplexer 2 is coupled to the input of a transmission gate 5 which passes the input to the output when CLK is low (CLKZ high) and is high impedance when CLK is high (CLKZ low). The output of the transmission gate 5 is coupled to the input of latch 6, that latch comprising an inverter 7 and a tristate inverter 8. Inverter 7 inverts the output of transmission gate 5 and tristate inverter 8 inverts the output of inverter 7 when CLK is high. The output of tristate inverter 8 is coupled to the input of inverter 7, thereby creating a feedback loop when CLK is high. The output of the tristate inverter is high impedance when CLK is low so that the feedback loop is broken when CLK goes from high to low.
The output of latch 6 is coupled to the input of a second transmission gate 9, that transmission gate passing the output of latch 6 when CLK is high and blocking that output signal when CLK is low. The output of transmission gate 9 is coupled to the input of a second latch 10 comprising an inverter 11 and a tristate inverter 12. The output of the transmission gate 9 is coupled to the input of inverter 11 and the output of inverter 11 is coupled to the input of tristate inverter 12. That tristate inverter 12 acts as an inverter when CLK is low and is high impedance when CLK is high. The output of the tristate inverter 12 is coupled to the input of inverter 11. Thus the second latch 10 is functionally equivalent to the first latch 6, except that the control signals for the tristate inverters 8 and 12 are connected so that when the feedback loop is connected in latch 6 it is disconnected in latch 10 and vice versa.
The output of the latch 10 (i.e. the output of inverter 11) is coupled to inverters 13 and 14 to provide the SQ and Q outputs respectively. The input to latch 10 (i.e. the output of transmission gate 9) is coupled to an inverter 15 to provide the QZ output.
The operation of the scannable flip-flop of FIGS. 1 and 2 will now be described with reference to the schematic of FIG. 2 and the timing diagram of FIG. 3. A number of nodes in the circuit of FIG. 2 have been labelled and the voltages at those nodes are shown in FIG. 3. Node U is the output of multiplexer 2, Node V is the output of transmission gate 5, node W is the output of latch 6, node X is the output of transmission gate 9 and node Y is the output of latch 10.
The timing diagram of FIG. 3 assumes that the ScanZ input is high so that the output of the multiplexer 2 is the inverse of the D input.
The D input shown in the timing diagram of FIG. 3 is initially high, falls whilst the CLK signal is low and rises again whilst the CLK signal is high. This is to illustrate the behaviour in the general case when the D signal is asynchronous with the CLK signal. Node U is simply the inverse of the D input. The voltage at node V is dependent on the transmission gate 5 and the tristate inverter 8. When CLK is low, the voltage at V follows the voltage at U. When CLK is high, the voltage at V follows the output of tristate inverter 8. When CLK is high, the output of tristate inverter 8 is the inverse of signal W.
In the example of FIG. 3, V is initially low since both CLK and U are low; W is high. When CLK goes high, V is the inverse of W and therefore remains low. When U rises, V rises at the same time (subject to a propagation delay through the transmission gate 5). W therefore falls at the same time. Now when CLK is high, V remains high as it follows the inverse of W. When the value of U falls, CLK is high so that the transmission gate is non-conducting, therefore V remains high (the inverse of W) until CLK is low. The falling edge of V is therefore delayed so that it is synchronised with the falling edge of CLK. Thus far, the rising edge of D has not, however, been synchronised with the CLK signal.
When CLK is high, the voltage at X follows the voltage at W. When CLK is low, the voltage at X is the inverse of signal Y. Thus X is initially high since W is high (the circuit is assumed to be stable at the start of the timing diagram). When CLK and W are both low, X is the inverse of Y and therefore remains high. X remains high until CLK rises again since when CLK is high, X follows W, which is already low and therefore pulls X low. W rises again at the same time as CLK falls. Thus W rises at the same time as transmission gate 9 becomes non-conducting. Thus X does not follow W at this point but stays low (being the inverse of Y). It is not until CLK rises, so that X once again follows W, that X rises. Therefore both the rising and falling edges of X are synchronised with the rising edge of the CLK signal.
The remainder of the circuit performs simple inversions so that at each rising edge of the CLK signal, the Q output takes on the value of the D input and the QZ output takes on the inverse of that D input.
FIG. 4 shows a transistor level implementation of the scannable flip-flop of FIGS. 1 and 2. The circuit comprises a plurality of NMOS transistors (N1 to N15) and a plurality of PMOS transistors (P1 to P15). Each transistor comprises a gate input, a source input and a drain input.
The gate input of transistor N1 is coupled to the gate input of P1 and to the D input. The gate of transistor P2 is coupled to the Scan input and the gate of transistor N2 is coupled to the ScanZ input. The source of P2 is coupled to the voltage supply VDD, the drain of P2 is coupled to the source of P1, the drain of P1 is coupled to the drain of N1, the source of N1 is coupled to the drain of N2 and the source of N2 is coupled to the voltage supply VSS. The drain of P1 and the drain of N1 are also coupled to the drain of P3 and the drain of N3. The source of P3 is coupled to the drain of P4 and the source of P4 is coupled to the voltage supply VDD. The source of N3 is coupled to the drain of N4 and the source of N4 is coupled to the voltage supply VSS. The gates of P3 and P4 are connected to ScanZ and SD respectively and the of N3 and N4 are connected to Scan and SD respectively. The transistors N1 to N4 and P1 to P4 collectively make up the multiplexer 2 of FIG. 2.
The drain of P3 and the drain of N3 are also coupled to the drain of P5 and the drain of N5. The source of N5 is coupled to the source of P5. The gates of N5 and P5 are connected to CLKZ and CLK respectively. Transistors N5 and P5 make up the transmission gate 5 of FIG. 2.
The source of N5 and the source of P5 are also coupled to the gate of N6 and gate of P6. The source of P6 is coupled to the voltage supply VDD, the drain of P6 is coupled to the drain of N6 and the source of N6 is coupled to the voltage supply VSS. The drain of N6 and the drain of P6 are also coupled to the gate of N8 and the gate of P8. The gates of N7 and P7 are coupled to CLK and CLKZ respectively. The source of P8 is coupled to the voltage supply VDD, the drain of P8 is coupled to the source of P7, the drain of P7 is coupled to the drain of N7, the source of N7 is coupled to the drain of N8 and the source of N8 is coupled to the voltage supply VSS. The drain of P7 and the drain of N7 are also coupled to the source of P5, the source of N5, the gate of P6 and the gate of N6. The transistors N6 to N8 and P6 to P8 make up the latch 6 of FIG. 2.
The drain of P6, the drain of N6, the gate of P8 and the gate of N8 are also coupled to the drain of P9 and the drain of N9. The source of N9 is coupled to the source of P9. The gates of N9 and P9 are connected to CLK and CLKZ respectively. Transistors N9 and P9 make up the transmission gate 9 of FIG. 2.
The source of N9 and the source of P9 are also coupled to the gate of N10 and the gate of P10. The source of P10 is coupled to the voltage supply VDD, the drain of P10 is coupled to the drain of N10 and the source of N10 is coupled to the voltage supply VSS. The drain of N10 and the drain of P10 are also coupled to the gate of N12 and the gate of P12. The gates of N11 and P11 are coupled to CLKZ and CLK respectively. The source of P12 is coupled to the voltage supply VDD, the drain of P12 is coupled to the source of P11, the drain of P11 is coupled to the drain of N11, the source of N11 is coupled to the drain of N12 and the source of N12 is coupled to the voltage supply VSS. The drain of P11 and the drain of N11 are also coupled to the source of P9, the source of N9, the gate of P10 and the gate of N10. The transistors N10 to N12 and P10 to P12 make up the latch 10 of FIG. 2.
The drain of P10, the drain of N10, the gate of P12 and the gate of N12 are coupled to the gates of transistors N13, N14, P13 and P14. The source of P13 is coupled to the voltage supply VDD, the drain of P13 is coupled to the drain of N13 and the source of N13 is coupled to the voltage supply VSS. The source of P14 is coupled to the voltage supply VDD, the drain of P14 is coupled to the drain of N14, the source of N14 is coupled to the voltage supply VSS. The drain of P13 and the drain of N13 are also coupled to the SQ output. The drain of P14 and N14 are also coupled to the Q output.
The source of P9, the source of N9, the gate of P10 and the gate of N10 are also coupled to the gate of P15 and the gate of N15. The source of P15 is coupled to the voltage supply VDD, the drain of P15 is coupled to the drain of N15 and the source of N15 is coupled to the voltage supply VSS. The drain of P15 and the drain of N15 are also coupled to the QZ output.
A scannable asynchronous preset and/or clear flip-flop having two latch circuits. The first latch circuit comprises an inverter and a tristate NAND gate. The second latch circuit comprises an inverter and a tristate NOR gate. When the CLK (clock input signal) and CLRZ (the inverse of the clear input signal) are both low, the output of the tristate NOR gate is forced low. Thus the input of inverter is low so that the output signal, Q, is forced low and the inverse output signal, QZ, is forced high. When CLK is high and CLRZ is low the output of tristate NAND gate is forced high so that the input to inverter is high and the input to inverter is low, thereby forcing Q low and QZ high. Thus the outputs Q and QZ are forced low and high respectively when CLRZ is low, regardless of the state of the CLK input.